1. Field of the Invention
The present invention relates to a voltage-booster power supply circuit. In particular, the present invention relates to a voltage-booster power supply circuit that is applicable to a semiconductor device requiring a voltage higher than a power supply voltage.
2. Description of Related Art
An internal circuit of a semiconductor device often requires a voltage higher than a power supply voltage. In such a case, a voltage-booster power supply circuit is used which supplies the voltage higher than the power supply voltage to the internal circuit of the semiconductor device. An example of the voltage-booster power supply circuit is described in Japanese Laid Open Patent Application JP-Heisei-9-163721 (JP-P1997-163721).
In the voltage-booster power supply circuit described in the above-mentioned patent document, first and second drive circuits for generating voltages are respectively connected to first and second charge pump circuits, and outputs of the first and second charge pump circuits are made common (configured to be complementary). Consequently, the two charge pump circuits operate while mutually cancelling a voltage ripple. It is thus possible to suppress the voltage ripple appearing in an output voltage and to supply a stable voltage.
Examples requiring a voltage-booster power supply circuit include a case where a voltage higher than the power supply voltage is applied to a word line. The examples also include a case where a voltage higher than the power supply voltage is applied to an anti-fuse. Such an example will be described below.
FIG. 1 illustrates an example of a configuration of a voltage-booster power supply circuit. The voltage-booster power supply circuit shown in FIG. 1 includes a semiconductor integrated circuit 105 and an external circuitry 106. A target circuit 7 as a power supply target is connected to the voltage-booster power supply circuit.
The semiconductor integrated circuit 105 is provided with a control circuit 101 and charge pump circuits 103-1 and 103-2. The control circuit 101 is connected to the charge pump circuits 103-1 and 103-2. The power supply voltage VDD is supplied to the charge pump circuits 103-1 and 103-2. The charge pump circuit 103-1 has a voltage output terminal Out1 and output terminals C1+ and C1−. The charge pump circuit 103-2 has a voltage output terminal Out2 and output terminals C2+ and C2−.
The external circuitry 106 is provided with a smoothing capacitor C0 and pumping capacitors C1 and C2. The smoothing capacitor C0 has positive and negative electrodes. Applied to the negative electrode is a common voltage Vcom as a reference voltage lower than the power supply voltage VDD. The positive electrode is connected to the voltage output terminal Out1 of the charge pump circuit 103-1, the voltage output terminal Out2 of the charge pump circuit 103-2 and the target circuit 7. The pumping capacitor C1 has positive and negative electrodes.
The positive and negative electrodes are connected to the output terminals C1+ and C1− of the charge pump circuit 103-1, respectively. The pumping capacitor C2 has positive and negative electrodes. The positive and negative electrodes are connected to the output terminals C2+ and C2− of the charge pump circuit 103-2, respectively.
The control circuit 101 outputs control signals Cnt1 and Cnt2, which are out-of-phase with each other, to the charge pump circuits 103-1 and 103-2, respectively, so as to complementarily operate the two charge pump circuits 103-1 and 103-2. For example, the control signal Cnt2 is a reversed phase control signal with respect to the control signal Cnt1. In response to the control signal Cnt1, the charge pump circuit 103-1 boosts a first voltage (power supply voltage VDD) with the use of the pumping capacitor C1 to generate a second voltage VDD2. In response to the control signal Cnt2, the charge pump circuit 103-2 boosts the first voltage (power supply voltage VDD) with the use of the pumping capacitor C2 to generate the second voltage VDD2. The second voltage VDD2 is smoothed by the smoothing capacitor C0 and then supplied as a third voltage to the target circuit 7.
Let us consider a case where a signal level of the control signal Cnt1 is low (L) level and that of the control signal Cnt2 is high (H) level. In this case, the charge pump circuit 103-1 applies the common voltage Vcom to the output terminal C1−, applies the first voltage VDD to the output terminal C1+, and thereby accumulates charges corresponding to the voltage difference (VDD−Vcom) in the pumping capacitor C1. On the other hand, charges corresponding to the voltage difference are being accumulated in the pumping capacitor C2, and the charge pump circuit 103-2 applies the first voltage VDD to the output terminal C2−. Consequently, the second voltage VDD2 that is obtained by adding the voltage difference (VDD−Vcom) to the first voltage VDD is applied to the output terminal C2+. The charge pump circuit 103-2 outputs the second voltage VDD2 to the voltage output terminal Out2. The second voltage VDD2 is smoothed by the smoothing capacitor C0 and then supplied as the third voltage to the target circuit 7.
Similarly, let us consider a case where a signal level of the control signal Cnt2 is low (L) level and that of the control signal Cnt1 is high (H) level. In this case, the charge pump circuit 103-2 applies the common voltage Vcom to the output terminal C2−, applies the first voltage VDD to the output terminal C2+, and thereby accumulates charges corresponding to the voltage difference (VDD−Vcom) in the pumping capacitor C2. On the other hand, charges corresponding to the voltage difference are being accumulated in the pumping capacitor C1, and the charge pump circuit 103-1 applies the first voltage VDD to the output terminal C1−. Consequently, the second voltage VDD2 that is obtained by adding the voltage difference (VDD−Vcom) to the first voltage VDD is applied to the output terminal C1+. The charge pump circuit 103-1 outputs the second voltage VDD2 to the voltage output terminal Out1. The second voltage VDD2 is smoothed by the smoothing capacitor C0 and then supplied as the third voltage to the target circuit 7.
For example, the target circuit 7 includes: a display unit in which a plurality of pixels are arranged in a matrix form; a plurality of gate lines respectively connected with a plurality of pixel rows of the display unit; and a plurality of data lines respectively connected with a plurality of pixel columns of the display unit. In this case, the semiconductor integrated circuit 105 is a driver IC that retrieves a display data from the outside and displays it on the display unit. The above-mentioned third voltage is applied to a selected gate line out of the plurality of gate lines.
Alternatively, the target circuit 7 may include: a memory unit and a fuse circuit. The memory unit has a plurality of memory cells and a redundant memory cell group. The fuse circuit has an anti-fuse group that is used for replacing a defect memory cell group in the plurality of memory cells with the redundant memory cell group. In this case, the semiconductor integrated circuit 105 is a driver IC for reading/writing data from/to the memory unit. The above-mentioned third voltage is applied to a selected anti-fuse out of the anti-fuse group.
As described above, the voltage-booster power supply circuit can apply the voltage higher than the power supply voltage VDD to the gate line (word line) or the anti-fuse. Here, the two charge pump circuits 103-1 and 103-2 are respectively connected to the two pumping capacitors C1 and C2 that are external components in the external circuitry 106, and the voltage-booster power supply circuit operate the charge pump circuits 103-1 and 103-2 in a complementary manner. As a result, according to the above voltage-booster power supply circuit, a higher current supply capability can be obtained as compared with a case where only one charge pump circuit 103-1 connected to one pumping capacitor C1 as the external component is operated.